1. Field of the Invention
The present invention relates to semiconductor structures and, more particularly, to a semiconductor structure with galvanic isolation.
2. Description of the Related Art
Galvanic isolation refers to an isolation that prevents a first system from communicating with a second system by way of a flow of electrons from one system to the other system, but which allows the two systems to communicate in other ways. For example, the first system can transmit a signal to the second system using changes in inductance or capacitance, or by using optical or other means.
Galvanic isolation is typically implemented with a dielectric layer that lies between and electrically isolates a first conductor, such as the first coil of a transformer or the first plate of a capacitor, and a second conductor, such as the second coil of the transformer or the second plate of the capacitor. Galvanic isolation is commonly used in multi-die chips that operate with different ground potentials and require a large isolation voltage, such as 5000VRMS.
FIG. 1 shows a plan view that illustrates an example of a prior-art, galvanically-isolated, multi-die chip 100. As shown in FIG. 1, chip 100 includes a lead frame 110 that has a high-voltage die attach pad or paddle (DAP) 112, and a low-voltage DAP 114 that is electrically isolated from high-voltage DAP 112. Conventional two-DAP lead frames commonly have a DAP-to-DAP spacing X of 0.5 mm.
As further shown in FIG. 1, multi-die chip 100 also includes a high-voltage die 120 that has high-voltage circuitry and signals, a galvanic isolation die 122, and a low-voltage die 124 that has low-voltage circuitry and signals. High-voltage die 120 and galvanic isolation die 122 are both physically connected to DAP 112 of lead frame 110, while low-voltage die 124 is physically connected to DAP 114 of lead frame 110.
In the present example, galvanic isolation die 122 utilizes changes in capacitance to transmit signals and, as a result, includes a capacitor for each signal to be transmitted. (Only one signal path or channel and one capacitor are shown for clarity.) Each capacitor, in turn, includes a high-voltage plate 130 that is electrically connected to a corresponding bond pad BP on high-voltage die 120 by way of a bonding wire BW, a low-voltage plate 132 that is electrically connected to a corresponding bond pad BP on low-voltage die 124 by way of a bonding wire BW, and a dielectric layer 134 that lies between and touches high-voltage plate 130 and low-voltage plate 132. In the present example, dielectric layer 134 can withstand a plate 130-to-plate 132 voltage difference of 5000VRMS without suffering dielectric breakdown.
In operation, high-voltage die 120 transmits data to low-voltage die 124 by encoding the data, and then placing encoded data signals in the form of pulses, RF waveforms, or glitches onto high-voltage plate 130. The signals are capacitively coupled to low-voltage plate 132, and are then detected and decoded by low-voltage die 124. (Alternately, capacitor die 122 could be replaced with a die having a transformer.)
One of the drawbacks of multi-die chip 100 is that a two-DAP lead frame requires a custom frame design, which is expensive and complicates the build process when compared to a standard single-DAP lead frame. Another drawback of multi-die chip 100 is that a two-DAP lead frame can be larger than a single-DAP lead frame. Thus, there is a need for an approach to providing galvanic isolation in a multi-die chip.